TTTC's Electronic Broadcasting Service

CALL FOR PAPERS AND PARTICIPATION

Scope -- Submissions -- Key Dates -- Additional Information -- Committee

Scope

It�s all about the DATA. Everything we do in Test relies on data. We use data to identify our good parts, our bad parts, and our weak parts We manipulate test data to detect outliers and reliability risks. We use data to control and adjust future testing. We also use data to record the full history of wafer lots and to track baseline production changes. And of course we have to collect all that data, store it, analyze it, secure it, and syndicate it to authorized consumers.

The Organizing Committee for the DATA-2014 Workshop is soliciting papers in the area of semiconductor test data management, analysis, and syndication. Of particular interest are innovations and advancements in: application of �Big Data� analysis techniques to test data, semiconductor test data acquisition methods, data storage and retrieval, security and syndication, analysis methods including data mining, and implementation of adaptive test. Submissions from qualified data management parties outside the semiconductor industry are welcome. Preference will be given to real-world case studies.

Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions and Poster style �Spot-Light� presentations describing industrial experiences or research are also invited.

Suggested Topics:
Data storage and security
Analog Fault modeling and coverage
Analog effects in Digital Logic
Embedded Instrumentation (iJTAG)
Advanced Product Engineering Techniques
Product and Project Case studies
Advanced dppm reduction techniques
Dynamic test elimination based on data
Adaptive Test for Product Engineers
Data Analysis methods, including multivariate data
Fault Localization and Diagnosis
Yield Learning and Analysis
I/O Test, Tuning, and Adjustment
Analysis of Aging and Reliability

Submissions

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To present at the workshop, send to JLRoehr@TI.com a PDF version of an extended abstract or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format ) by September 15, 2014. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Oct 10, 2014.

Key Dates

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Submission Deadline: September 15, 2014 (EXTENDED)

Notification of Acceptance: October 1, 2014

Camera Ready Paper (.pdf): October 10, 2014

Final Presentation Slides (.ppt): October 15, 2014

Additional Information

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Technical Program Submissions:

Jeffrey Roehr

Texas Instruments, USA.

E-mail: JLRoehr@TI.com

General Information:

Arani Sinha

Intel, USA.

E-mail: Arani.Sinha@INTEL.com

Committee

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GENERAL CHAIR

Arani Sinha, Intel

PROGRAM CHAIR

Jeffrey Roehr, Texas Instruments

VICE-PROGRAM CHAIR

Jennifer Dworak, SMU

PANEL CHAIR

Wesley Smith, Galaxy

FINANCE CHAIR

Sankaran Menon, Intel

PUBLICITY CHAIR

Kanad Chakraborty, Lattice Semi

PUBLICATIONS CHAIR

Chintan Patel, UMBC

TEST STANDARDS CHAIR

Al Crouch, ASSET InterTech

EU LIAISON

Paul Simon, Qualtera

STEERING COMMITTEE

Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Star Test
Jim Plusquellic, U. New Mexico

PROGRAM COMMITTEE

Rob Aitken, ARM
Nemat Bidokhti, Cisco
Sreejit Chakravarty, LSI
John Carulli, TI
Patrick Girard, LIRMM, France
Ajay Khoche, Consultant
Mike Laisne, Qualcomm
Amit Nahar, TI
Suriyaprakash Natarajan, Intel
Jay Orbon, Consultant
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Claude Thibeault, ETS, Canada
Li C. Wang, UCSB
Xiaoqing Wen, KIT, Japan
Qiang Xu, CUHK, Hong Kong

For more information, visit us on the web at: http://DATA.tttc-events.org/

The IEEE International Workshop on Defects, Adaptive Test and Data Analysis 2014 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).